|Open Verification Methodology||Specification||
Description: Mentor Graphics and Cadence Design Systems collaborated on the "Open Verification Methodology", which they have now offered up for public consumption. The OVM website states "The OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and is interoperable with multiple languages and simulators. The OVM is fully open, and includes a robust class library and source code that is available for download."
Author(s): Mentor Graphics and Cadence Design Systems
Format: HTML, Other
Limitations: You will need to register before downloading the OVM libraries. Acknowledgement of registration is NOT immediate (come on guys!); so you may have to wait a while after registering before you can download files.
Keywords: Verilog , System Verilog , verification , Mentor Graphics , Cadence Design Systems , OVM
Submitter: EE HomePage Editorial Staff
xml_ID: 1205291289 (single entry page)
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