|Implementation of a DFM checker for 65nm and beyond||Article||
Description: This is a nice five page introduction (from the EDA Tech Forum) to Design for Manufacturability at 65nm and below by engineers at the Crolles2 Alliance (Freescale Semiconductor, NXP Semiconductors and STMicroelectronics).
Author(s): Le Maitre, P. & Simon, P. & Goncalves, R & Le Cam, L. & de Vries, D. & Bernard-Granger, F. & Parmentier, F. & Bingert, R. & Marin, J.-C. & Boone, R. & Hours, X.
Format: Paper, PDF
URL: http://www.edatechforum.com/ journal/ june2007/ implementation_intro.cfm
Limitations: You will have to register on the EDA Tech Forum web site to gain full access to the article (free).
ReviewText: This article introduces DFM metrics and guidelines and discusses how improving one metric may adversely affect others - and how to hit the optimal mix.
Keywords: SoC , DRC , DFM , design for manufacturability , yield , design rule checks , Calibre
Submitter: EE HomePage Editorial Staff
xml_ID: 1180237119 (single entry page)
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