| Name | Type | Details |
| EE 5/418 Memory Circuit Design | Webcast |
Description: Pre-recorded Memory Design Course from Boise State University, taught by Jake Baker. This is a full college course (27 lectures) on the subject. All lectures available in video format, with accompanying PDFs showing whiteboard drawings by Mr. Baker.
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Author(s): Baker, Jake License: Unknown Format: PDF, Video Price: Free URL: http://cmosedu.com/ jbaker/ courses/ ee5418/ s07/ notes/ lec5418.htm Keywords: circuit design , Spice , PLL , DRAM , flash memory , DLL , college courses , DDR , SRAM , SDRAM , memory design , sense amps , delay-locked loops , VCO , phase locked loops Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1178389525 (single entry page) |
| International Technology Roadmap for Semiconductors | Specification |
Description: "The International Technology Roadmap for Semiconductors, known throughout the world as the ITRS, is the fifteen-year assessment of the semiconductor industry's future technology requirements."
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Author(s): Consortium License: Commercial Format: PDF Price: free online URL: http://www.itrs.net/ ReviewText: This is the site to go to if you want to consult the best crystal ball that the semiconductor business has to offer. We're not sure how we missed listing it in the EE HomePage.com databases before now. The reports are quite detailed. If you are in the business, you need to check this one out. Keywords: semiconductor , manufacturing , wireless , simulation , lithography , packaging , interconnect , roadmap , ITRS , ESIA , JEITA , KSIA , TSIA , SIA , DRAM , flash memory , gate length , modeling , process integration , yield enhancement , metrology Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1169950339 (single entry page) |
| A Fully Associative Software-Managed Cache Design | Article |
Description: "This paper has two primary contributions: a practical design
for a fully associative memory structure, the indirect index cache (IIC), and a novel replacement algorithm, generational replacement, that is specifically designed to work with the IIC."
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Author(s): Hallnor, Erik G. & Reinhardt, Steven K. License: Commercial Format: PDF Price: Free URL: http://www.eecs.umich.edu/ ~stever/ pubs/ isca00-iic.pdf ReviewText: 10 pages. Analysis includes some rather nice charts of cache misses vs. associativity , LRU and OPT Keywords: IIC , DRAM , cache , fully associative memory , indirect index cache , LRU , memory latency , access time , set-associate cache Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1170815482 (single entry page) |
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