| Name | Type | Details |
| EE 5/410 Integrated Circuit Physical Design | Webcast |
Description: Pre-recorded IC Physical Design Course from Boise State University, taught by Jake Baker. This is a full college course (27 lectures) on the subject. All lectures available in video format, with accompanying PDFs showing whiteboard drawings by Mr. Baker.
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Author(s): Baker, Jake License: Unknown Format: PDF, Video Price: Free URL: http://www.cmosedu.com/ jbaker/ courses/ ee5410/ s07/ notes/ lec5410.htm Keywords: Spice , place & route , CAD , layout , DRC , IRSIM , LVS , MOSFET , LTSPICE , WinSpice , college courses , transmission gate , ALS , ring oscillators , delay equations Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1178389125 (single entry page) |
| PCB Design Tutorial | Tutorial |
Description: 25 page tutorial that starts from the basics of design of printed circuit boards.
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Author(s): Jones, David L. License: Some Restrictions (includes GNU) Format: PDF Price: free download URL: http://www.pcb123.com/ tutorials/ PDF% 20Documents/ PCBDesignTutorialRevA.pdf ReviewText: The author's goal was to "take some of the mystery out of PCB design." This looks like an excellent primer. Keywords: PCB , layout , DRC , silk screen , solder mask , high frequency design Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1153706434 (single entry page) |
| Implementation of a DFM checker for 65nm and beyond | Article |
Description: This is a nice five page introduction (from the EDA Tech Forum) to Design for Manufacturability at 65nm and below by engineers at the Crolles2 Alliance (Freescale Semiconductor, NXP Semiconductors and STMicroelectronics).
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Author(s): Le Maitre, P. & Simon, P. & Goncalves, R & Le Cam, L. & de Vries, D. & Bernard-Granger, F. & Parmentier, F. & Bingert, R. & Marin, J.-C. & Boone, R. & Hours, X. License: Commercial Format: Paper, PDF Price: Free URL: http://www.edatechforum.com/ journal/ june2007/ implementation_intro.cfm Limitations: You will have to register on the EDA Tech Forum web site to gain full access to the article (free). ReviewText: This article introduces DFM metrics and guidelines and discusses how improving one metric may adversely affect others - and how to hit the optimal mix. Keywords: SoC , DRC , DFM , design for manufacturability , yield , design rule checks , Calibre Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1180237119 (single entry page) |
| Name | Type | Details |
| Alli@nce VLSI CAD System | VLSI Development |
Description: The Alli@nce homepage says it best: "Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.
"
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License: Open Source, GNU or similar Price: free URL: http://www-asim.lip6.fr/ recherche/ alliance/ doc/ design-flow/ tools.html OSs: Windows, Linux, Solaris, Source Available Limitations: Binaries, source code and cell libraries are available under the GNU General Public License (GPL). ReviewText: The Alli@ance Tools Overview page does a great job of specifying the strengths and weaknesses of each tool in the CAD system. We'll limit ourselves here to simply listing the tools:
Keywords: VHDL , CIF , GDS , simulator , place & route , CAD , DRC , RTL , schematic , standard cells , RAM , ROM , Alliance CAD , formal proof , formal verification , logic synthesis , data-path , netlist extraction , FSM , layout editor , equivalence checker Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1150681894 (single entry page) |
No matching Orgs were found.