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"GALS" references for the Electrical Engineer
Entries 1 through 5 of 5 were returned.
| Name |
Type |
Details
|
| Asynchronous Techniques for System-On-Chip Design
|
Tutorial |
Description: An invited paper from the June 2006 Proceedings of the IEEE.
[show less...]
Author(s): Martin, Alain J.
& Nystrom, Mika
License: PublicDomain
Format: PDF
Price: Free
URL: http://www.async.caltech.edu/ Pubs/ PDF/ 2006_ieee_soc.pdf
ReviewText: 32 pages long, looks like a great introduction to the topic.
Keywords: SoC
, GALS
, asynchronous logic
, globally asynchronous locally synchronous
, System-On-Chip
, dual rail logic
, PCHB
, QDI
, synchronizer
Submitter: EE HomePage Editorial Staff
Affiliation: None
xml_ID: 1170128019 ( single entry page)
|
| Design and Testing of a Simple GALS Circuit
|
White Paper |
Description: This 42-page academic report describes the design of a Globally Asynchronous Locally Synchronous (GALS) design.
[show less...]
Author(s): Blaauwendraad, Bart
License: Some Restrictions (includes GNU)
Format: PDF
Price: free
URL: http://www.google.com/ url? sa=t& amp;ct=res& amp;cd=10& amp;url=http% 3A% 2F% 2Fwww.diva-portal.org% 2Fdiva% 2FgetDocument% 3Furn_nbn_se_liu_diva-1258-1__fulltext.pdf& amp;ei=aLe-RcylIIX8ggOqmKSYCw& amp;usg=__CvsVRe5aOBveM8uQoG55vd7BDw4=& amp;sig2=BvCJ1kP2Zsw2hC-FHZn4XA
Keywords: GALS
, asynchronous logic
, synchronous logic
, Muller C-element
, BIST
, globally asynchronous locally synchronous
, IDDQ
, scan-path testing
, stuck-at
, stuck-open
Submitter: EE HomePage Editorial Staff
Affiliation: None
xml_ID: 1170127197 ( single entry page)
|
| Asynchronous Wrapper for Globally Asynchronous Locally Synchronous Systems
|
Thesis |
Description: 45 page thesis with the goal of building an asynchronous wrapper in VHDL and then testing same in an FPGA.
|
| Asynchronous Network-on-Chip Architecture Performance Analysis
|
Thesis |
Description: 63 page Master's thesis exploring performance characteristics of a GALS network.
|
| Globally-Asynchronous, Locally-Synchronous Wrapper Configurations For Point-To-Point and Multi-Point Data Communication
|
Thesis |
Description: 167 page Master's Thesis intended as an introduction to GALS design techniques.
|
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