| Name | Type | Details |
| Project Veripage | Web-Site |
Description: Web site with a variety of resources for Verilog and System Verilog users.
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Author(s): Various License: Commercial URL: http://www.project-veripage.com/ ReviewText: Contains quite a few tutorials on specific subjects. Keywords: Verilog , HDL , System Verilog , simulation , assertions , property specification language , PSL , PLI , IP cores Submitter: EE HomePage Editorial Staff Affiliation: Reader xml_ID: 1153701155 (single entry page) |
| Verilog Links from ASIC World.com | Web-Site |
Description: Another great site for anyone wanting to learn more about Verilog.
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Author(s): Various License: Unknown Format: PDF, HTML Price: free download URL: http://www.asic-world.com/ verilog/ verilinks.html Limitations: This site has a mixture of free and commercial content. ReviewText: We wouldn't include it here if we didn't think it was worth a visit. This, coupled with Project Veripage should give you more than enough material on the subject! Keywords: IEEE , Verilog , HDL , EDA , Verilog-AMS , PLI , simulators , VCD viewers , OVI , EMACS , XEMACS , code coverage , linting Submitter: EE HomePage Editorial Staff Affiliation: Reader xml_ID: 1154058009 (single entry page) |
| Name | Type | Details |
| Veriwell Verilog Simulator | Verilog simulator |
Description: Available in source format from SourceForge.
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License: Open Source, GNU or similar Price: free download URL: http://sourceforge.net/ projects/ veriwell OSs: Source Available Limitations: The README in the source distribution notes: "It is compliant to verilog 95, but does not fully support it. The most notable missing feature is the support for strengths." ReviewText: Supports nearly all of IEEE 1364-1995 and includes PLI 1.0 support. You might like to checkout a 2005 interview with the developer by EE Times. Keywords: Verilog , HDL , simulator , PLI , SourceForge , Veriwell Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1150510815 (single entry page) |
| Name | Type | Details |
| Accellera | Standards |
Description: From their website: "Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International to focus on identifying new standards, development of standards and formats, and to foster the adoption of new methodologies."
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Dues: $5k->$15K URL: http://www.accellera.org/ home/ Limitations: At the time of posting, annual corporate membership runs $15K per year. Associate membership is $5K per year. ReviewText: You can download the Accellera Open Verification Library (OVL). We went looking for VHDL and Verilog reference manuals, and couldn't find them. Keywords: Verilog , VHDL , PLI , OVI , SDF , Vital , RTL , Accellera Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1145131228 (single entry page) |