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"RTL" references for the Electrical Engineer
Entries 1 through 2 of 2 were returned.
Name Type Details
Web Seminars at Planet EE.com Webcast Description: Planet EE (Penton Electronics Group) hosts a number of on-demand webcasts at this site.
Unified Power Format Specification Description: From the UPF spec: "UPF provides the ability for electronic systems to be designed with power as a key consideration early in the process. It accomplishes this through the ability to allow the specification of implementation-relevant power information early in the design process RTL (register transfer level) or earlier."

"RTL" related tools for the Electrical Engineer
Entries 1 through 4 of 4 were returned.
Name Type Details
Alli@nce VLSI CAD System VLSI Development Description: The Alli@nce homepage says it best: "Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router. "
GOF: Gates On the Fly netlist processing Description: GOF is a graphical netlist processing tool which integrates a netlist browser, partial schematic and ECO capability.
SPARK C-to-VHDL high-level synthesis framework High level synthesis Description: "SPARK takes behavioral ANSI-C code as input, schedules it using speculative code motions and loop transformations, runs an interconnect-minimizing resource binding pass and generates a finite state machine for the scheduled design graph. Finally, a backend code generation pass outputs synthesizable register-transfer level (RTL) VHDL. This VHDL can then by synthesized using logic synthesis tools into an ASIC or by mapped onto a FPGA. "
C to Verilog High level synthesis Description: C to Verilog is an easy to use web-based service which accepts a C language description of your datapath and generates synthesizable Verilog output.

"RTL" related organizations for the Electrical Engineer
Entries 1 through 1 of 1 were returned.
Name Type Details
Accellera Standards Description: From their website: "Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International to focus on identifying new standards, development of standards and formats, and to foster the adoption of new methodologies."