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"Verilog" references for the Electrical Engineer
Entries 1 through 14 of 14 were returned.
Name EntryDate Details
Open Verification Methodology 2008-03-11 20:08:09 Description: Mentor Graphics and Cadence Design Systems collaborated on the "Open Verification Methodology", which they have now offered up for public consumption. The OVM website states "The OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and is interoperable with multiple languages and simulators. The OVM is fully open, and includes a robust class library and source code that is available for download."
Altium VHDL Language Reference 2007-09-18 20:15:56 Description: Altium has a 196 page VHDL Language Reference Manual available for download on their site. This reference discusses IEEE Standard 1164 and 1076.3. PDF bookmarks take you right to the VHDL keyword you're interested in.
Unified Power Format 2007-03-15 22:09:47 Description: From the UPF spec: "UPF provides the ability for electronic systems to be designed with power as a key consideration early in the process. It accomplishes this through the ability to allow the specification of implementation-relevant power information early in the design process RTL (register transfer level) or earlier."
OVI Verilog HDL LRM 2006-10-01 20:20:06 Description: This is Version 1.0 of the Verilog Language Reference Manual published in November, 1991. It has been superceded by the IEEE specifications.
All My Xs Come From Texas . . . Not!! 2006-10-01 19:12:10 Description: The title is irresistable, and the topic - avoiding unknowns in your Verilog simulations - is worthwhile too.
Standard Delay Format Specification Version 3.0 2006-09-10 20:12:12 Description: SDF, or Standard Delay Format, is the industry standard for annotating delays into Verilog simulations. This is the OVI specification for the format.
Verilog Links from ASIC World.com 2006-07-27 21:40:09 Description: Another great site for anyone wanting to learn more about Verilog.
Project Veripage 2006-07-23 18:32:35 Description: Web site with a variety of resources for Verilog and System Verilog users.
Application-Specific Integrated Circuits 2006-06-16 18:54:22 Description: This text (offered online by edatoolscafe.com) covers the basics of ASIC technologies.
Verilog-A/MS 2006-05-11 22:32:33 Description: The Designer's Guide web page for Verilog-A/MS is exceptionally well organized and worth a look if you are using Verilog-AMS.
Introduction to Verilog 2006-04-15 19:11:29 Description: This is a very nice 33-page introduction to Verilog with lots of examples.
Verilog Reference Manual 2006-04-15 14:46:40 Description: Basic Verilog Overview
Computer Aids for VLSI Design 2006-04-15 14:38:36 Description: Design environments, synthesis, static timing analysis, etc.
Verilog HDL On-line Quick Reference 2006-04-15 13:11:39 Description: A concise summary of the language by Stuart Sutherland. Can be viewed online or downloaded.

"Verilog" related tools for the Electrical Engineer
Entries 1 through 11 of 11 were returned.
Name EntryDate Details
C to Verilog 2009-07-04 14:48:55 Description: C to Verilog is an easy to use web-based service which accepts a C language description of your datapath and generates synthesizable Verilog output.
SynaptiCAD 2009-03-23 23:35:21 Description: SynaptiCAD makes a family of CAD tools for use on Linux, Solaris & Windows. Current products include:
  • TestBencher
  • BugHunter
  • VeriLogger
  • Waveformer
  • Timing Diagrammer
  • HDL Tranlators
  • GigaWave Viewer
  • HDL Companion
Quartus II Web Edition Software from Altera 2007-05-24 19:01:19 Description: Like many vendors, Altera has both free and subscription versions of their design software available. Check their online comparison chart to see if the free version will suit your needs.
Libero FPGA Integrated Development Environment 2007-04-10 19:50:15 Description: Actel's website states: "Libero Integrated Design Environment (IDE) is Actel's comprehensive software toolset for designing with all Actel FPGAs. From schematic and/or HDL design, synthesis and simulation, through floorplanning, place and route, timing constraints and analysis, power analysis, and program file generation."
GOF: Gates On the Fly 2006-09-12 21:18:02 Description: GOF is a graphical netlist processing tool which integrates a netlist browser, partial schematic and ECO capability.
Veriwell Verilog Simulator 2006-06-16 19:20:15 Description: Available in source format from SourceForge.
Cver 2006-04-27 22:12:47 Description: An open source Verilog simulator which supports the full 1995 P1364 standard and some of the 2001 standard.
Electric VLSI Design System 2006-04-15 14:32:43 Description: From their website: "The ElectricTM VLSI Design System is a complete Electronic Design Automation (EDA) system that can handle many forms of circuit design".
VBS 1970-08-20 22:18:52 Description: Verilog Behavioral Simulator
Icarus Verilog 1970-08-20 22:18:43 Description: An open source Verilog compiler.
gnetlist 1970-08-20 22:18:35 Description: Part of the gEDA project, this tool converts gschem files into a number of formats: Unix PCB, Spice, Verilog VHDL and many others.

"Verilog" related organizations for the Electrical Engineer
Entries 1 through 1 of 1 were returned.
Name EntryDate Details
Accellera 2006-04-15 14:00:28 Description: From their website: "Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International to focus on identifying new standards, development of standards and formats, and to foster the adoption of new methodologies."