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"Verilog" references for the Electrical Engineer
Entries 1 through 14 of 14 were returned.
Name Type Details
Project Veripage Web-Site Description: Web site with a variety of resources for Verilog and System Verilog users.
Verilog Links from ASIC World.com Web-Site Description: Another great site for anyone wanting to learn more about Verilog.
Verilog HDL On-line Quick Reference Web-Page Description: A concise summary of the language by Stuart Sutherland. Can be viewed online or downloaded.
Verilog Reference Manual Web-Page Description: Basic Verilog Overview
Verilog-A/MS Links Page Description: The Designer's Guide web page for Verilog-A/MS is exceptionally well organized and worth a look if you are using Verilog-AMS.
Standard Delay Format Specification Version 3.0 Specification Description: SDF, or Standard Delay Format, is the industry standard for annotating delays into Verilog simulations. This is the OVI specification for the format.
OVI Verilog HDL LRM Specification Description: This is Version 1.0 of the Verilog Language Reference Manual published in November, 1991. It has been superceded by the IEEE specifications.
Unified Power Format Specification Description: From the UPF spec: "UPF provides the ability for electronic systems to be designed with power as a key consideration early in the process. It accomplishes this through the ability to allow the specification of implementation-relevant power information early in the design process RTL (register transfer level) or earlier."
Open Verification Methodology Specification Description: Mentor Graphics and Cadence Design Systems collaborated on the "Open Verification Methodology", which they have now offered up for public consumption. The OVM website states "The OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and is interoperable with multiple languages and simulators. The OVM is fully open, and includes a robust class library and source code that is available for download."
All My Xs Come From Texas . . . Not!! White Paper Description: The title is irresistable, and the topic - avoiding unknowns in your Verilog simulations - is worthwhile too.
Computer Aids for VLSI Design Book Description: Design environments, synthesis, static timing analysis, etc.
Application-Specific Integrated Circuits Book Description: This text (offered online by edatoolscafe.com) covers the basics of ASIC technologies.
Altium VHDL Language Reference Book Description: Altium has a 196 page VHDL Language Reference Manual available for download on their site. This reference discusses IEEE Standard 1164 and 1076.3. PDF bookmarks take you right to the VHDL keyword you're interested in.
Introduction to Verilog Book Description: This is a very nice 33-page introduction to Verilog with lots of examples.

"Verilog" related tools for the Electrical Engineer
Entries 1 through 11 of 11 were returned.
Name Type Details
SynaptiCAD Verilog simulator, timing diagrammer, etc. Description: SynaptiCAD makes a family of CAD tools for use on Linux, Solaris & Windows. Current products include:
  • TestBencher
  • BugHunter
  • VeriLogger
  • Waveformer
  • Timing Diagrammer
  • HDL Tranlators
  • GigaWave Viewer
  • HDL Companion
Cver Verilog simulator Description: An open source Verilog simulator which supports the full 1995 P1364 standard and some of the 2001 standard.
Veriwell Verilog Simulator Verilog simulator Description: Available in source format from SourceForge.
Icarus Verilog Verilog Description: An open source Verilog compiler.
VBS Verilog Description: Verilog Behavioral Simulator
GOF: Gates On the Fly netlist processing Description: GOF is a graphical netlist processing tool which integrates a netlist browser, partial schematic and ECO capability.
gnetlist Netlist Generation Description: Part of the gEDA project, this tool converts gschem files into a number of formats: Unix PCB, Spice, Verilog VHDL and many others.
Electric VLSI Design System IC Layout, Schematic Entry, Verilog, VHDL & FPGA Design Description: From their website: "The ElectricTM VLSI Design System is a complete Electronic Design Automation (EDA) system that can handle many forms of circuit design".
C to Verilog High level synthesis Description: C to Verilog is an easy to use web-based service which accepts a C language description of your datapath and generates synthesizable Verilog output.
Quartus II Web Edition Software from Altera CPLD & FPGA Design Software Description: Like many vendors, Altera has both free and subscription versions of their design software available. Check their online comparison chart to see if the free version will suit your needs.
Libero FPGA Integrated Development Environment Actel Integrated IDE for FPGA design Description: Actel's website states: "Libero Integrated Design Environment (IDE) is Actel's comprehensive software toolset for designing with all Actel FPGAs. From schematic and/or HDL design, synthesis and simulation, through floorplanning, place and route, timing constraints and analysis, power analysis, and program file generation."

"Verilog" related organizations for the Electrical Engineer
Entries 1 through 1 of 1 were returned.
Name Type Details
Accellera Standards Description: From their website: "Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International to focus on identifying new standards, development of standards and formats, and to foster the adoption of new methodologies."