| Name | Type | Details |
| Memory Hierarchy in Cache-Based Systems | Tutorial |
Description: "This article is to help the reader understand the architecture of modern
microprocessors. It introduces and explains the most common terminology and
addresses some of the performance related aspects."
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Author(s): van der Pas, Ruud License: Commercial Format: PDF Price: Free URL: http://www.sun.com/ blueprints/ 1102/ 817-0742.pdf ReviewText: roughly 20 pages long, this tutorial is published by Sun Microsystems (who presumably know something about the topic). Keywords: bandwidth , cache , virtual memory , memory hierarchy , TLB cache , latency , direct mapped cache , fully associative cache , set associative cache , software prefetch Submitter: EE HomePage Editorial Staff Affiliation: Employee xml_ID: 1170985609 (single entry page) |
| Cache Design for Embedded Real-Time Systems | Article |
Description: "This paper compares the operation and organization of
caches as found in general-purpose processors, microcontrollers,
and DSPs; it also discusses designs for embedded realtime
systems."
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Author(s): Jacob, Bruce License: Unknown Format: PDF Price: free URL: http://www.ee.umd.edu/ ~blj/ papers/ esc99.pdf ReviewText: 9 pages. Discusses traditional caches, basic cache mechanics, virtual memory, cache organization, advantages and disadvantages of caches, software managed organizations Keywords: ASIC , cache , virtual memory , real-time systems , memory hierarchy , embedded designs Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1170814973 (single entry page) |
| A Fully Associative Software-Managed Cache Design | Article |
Description: "This paper has two primary contributions: a practical design
for a fully associative memory structure, the indirect index cache (IIC), and a novel replacement algorithm, generational replacement, that is specifically designed to work with the IIC."
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Author(s): Hallnor, Erik G. & Reinhardt, Steven K. License: Commercial Format: PDF Price: Free URL: http://www.eecs.umich.edu/ ~stever/ pubs/ isca00-iic.pdf ReviewText: 10 pages. Analysis includes some rather nice charts of cache misses vs. associativity , LRU and OPT Keywords: IIC , DRAM , cache , fully associative memory , indirect index cache , LRU , memory latency , access time , set-associate cache Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1170815482 (single entry page) |
| PC Architecture | Book |
Description: Well illustrated (high level) text describing architecture of personal computers.
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Author(s): Karbo, Michael License: Some Restrictions (includes GNU) Format: HTML Price: Free for personal use URL: http://www.karbosguide.com/ ReviewText: Contents are:
Keywords: ISA , PCI , USB , SCSI , RAM , cache , PC , personal computer , Von Neumann , motherboard , CPU , north bridge , south bridge , FPU , SATA , ATA , Firewire Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1170996311 (single entry page) |
| Practical File System Design | Book |
Description: This is a 247 page textbook which delves into the practical aspects of file system design using the Be File System as an example implementation. This text was originally published by Morgan Kaufmann Publishers, Inc., and is now out of print. The online copy is found on the author's website.
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Author(s): Giampaolo, Dominic License: Commercial Format: Paper, PDF Price: Free URL: http://www.letterp.com/ ~dbg/ practical-file-system-design.pdf ReviewText: Discusses BFS and BeOS, explores alternate file systems like BSD FFS, Linux ext2, Macintosh HFS, etc. It covers data structures, attributes, indexing, allocation policies, journaling, caches and file system performance. Keywords: cache , BFS , BeOS , file systems , POSIX , Vnodes , journaling , I-Node Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1180375137 (single entry page) |
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