| Name | Type | Details |
| Asynchronous Techniques for System-On-Chip Design | Tutorial |
Description: An invited paper from the June 2006 Proceedings of the IEEE.
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Author(s): Martin, Alain J. & Nystrom, Mika License: PublicDomain Format: PDF Price: Free URL: http://www.async.caltech.edu/ Pubs/ PDF/ 2006_ieee_soc.pdf ReviewText: 32 pages long, looks like a great introduction to the topic. Keywords: SoC , GALS , asynchronous logic , globally asynchronous locally synchronous , System-On-Chip , dual rail logic , PCHB , QDI , synchronizer Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1170128019 (single entry page) |
| Asynchronous Circuit Design: A Tutorial | Book |
Description: From the book's preface: "This book was compiled to address a perceived need for an introductory text
on asynchronous design. There are several highly technical books on aspects of
the subject, but no obvious starting point for a designer who wishes to become
acquainted for the first time with asynchronous technology."
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Author(s): Sparso, Jens & Furber, Steve License: Some Restrictions (includes GNU) Format: PDF Price: Free for non-commercial use URL: http://www.ee.technion.ac.il/ courses/ 048878/ book.pdf Limitations: may be used unmodified and in its entirety for non-commercial educational purposes only. ReviewText: This is a 182 page draft copy. Keywords: low power , EMI , logic design , dual rail logic , asynchronous design , handshaking , Muller pipeline Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1174192664 (single entry page) |
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