Where EEs Navigate A Changing World.

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"formal verification" related tools for the Electrical Engineer
Entries 1 through 4 of 4 were returned.
Name Type Details
Alli@nce VLSI CAD System VLSI Development Description: The Alli@nce homepage says it best: "Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router. "
Gameplan Verification Planner Description: "GamePlan Verification Planner assists users in creating structured verification plans and tracking verification progress over the entire verification cycle."
ACL2 Version 3.0 programming language & theorem prover Description: A Computational Logic for Applicative Common Lisp (ACL2) - think of it as a framework for formal verification.
Quartus II Web Edition Software from Altera CPLD & FPGA Design Software Description: Like many vendors, Altera has both free and subscription versions of their design software available. Check their online comparison chart to see if the free version will suit your needs.

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