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| Name | Type | Details |
| Alli@nce VLSI CAD System | VLSI Development |
Description: The Alli@nce homepage says it best: "Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.
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License: Open Source, GNU or similar Price: free URL: http://www-asim.lip6.fr/ recherche/ alliance/ doc/ design-flow/ tools.html OSs: Windows, Linux, Solaris, Source Available Limitations: Binaries, source code and cell libraries are available under the GNU General Public License (GPL). ReviewText: The Alli@ance Tools Overview page does a great job of specifying the strengths and weaknesses of each tool in the CAD system. We'll limit ourselves here to simply listing the tools:
Keywords: VHDL , CIF , GDS , simulator , place & route , CAD , DRC , RTL , schematic , standard cells , RAM , ROM , Alliance CAD , formal proof , formal verification , logic synthesis , data-path , netlist extraction , FSM , layout editor , equivalence checker Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1150681894 (single entry page) |
| Gameplan | Verification Planner |
Description: "GamePlan Verification Planner assists users in creating structured verification plans and tracking verification progress over the entire verification cycle."
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License: Commercial Price: Free URL: http://www.jasper-da.com/ gameplan/ index.php OSs: Linux, Solaris ReviewText: This tool formalizes generation, maintenance and web-based presentation of verification plans. The company offers a number of products addressing the verification market. Making GamePlan freely available is a way to make customers aware of the other products. Keywords: assertions , XML , formal verification , verification , test coverage Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1174167873 (single entry page) |
| ACL2 Version 3.0 | programming language & theorem prover |
Description: A Computational Logic for Applicative Common Lisp (ACL2) - think of it as a framework for formal verification.
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License: Open Source, GNU or similar Price: free download URL: http://www.cs.utexas.edu/ users/ moore/ acl2/ OSs: Windows, Linux, Mac-OS, Source Available Limitations: The ACL2 website notes it can be used as "a programming language, a specification language, a modeling language, a formal mathematical logic, or a semi-automatic theorem prover." ReviewText: ACL2 is the winner of the 2005 ACM Software System Award. The list of ACL2 applications on the site is impressive. Keywords: formal verification , LISP , ACL2 , theorem prover , programming language , specification language Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1151905511 (single entry page) |
| Quartus II Web Edition Software from Altera | CPLD & FPGA Design Software |
Description: Like many vendors, Altera has both free and subscription versions of their design software available. Check their online comparison chart to see if the free version will suit your needs.
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License: Commercial Price: Free URL: https://www.altera.com/ support/ software/ download/ altera_design/ quartus_we/ dnl-quartus_we.jsp OSs: Windows Limitations: You have to renew the license after 150 days with the free version. ReviewText: See also the Quartus Software Support page on Altera's site for lots of good documentation and training materials. Keywords: Verilog , HDL , VHDL , STA , simulation , FPGA , synthesis , place & route , CAD , schematic capture , formal verification , ModelSim , floorplanning , CPLD Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1180058479 (single entry page) |
No matching Orgs were found.