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"low power CMOS" references for the Electrical Engineer
Entries 1 through 1 of 1 were returned.
|Energy Efficient Design for Deep Sub-micron CMOS VLSIs
Description: The abstract of this 2005 PhD Thesis from the University of Waterloo begins "Over the past decade, low power, energy efficient VLSI design has been the focal point
of active research and development. The rapid technology scaling, the growing integration
capacity, and the mounting active and leakage power dissipation are contributing to the
growing complexity of modern VLSI design. Careful power planning on all design levels is
required. This dissertation tackles the low-power, low-energy challenges in deep sub-micron
technologies on the architecture and circuit levels."
Author(s): Elgebaly, Mohamed
URL: http://etd.uwaterloo.ca/ etd/ mmelgeba2005.pdf
190 pages long. Contents include:
- Power Dissipation Components in Digital CMOS Circuits (switching and leakage)
- Power and Energy Reduction Techniques
- Supply Voltage Reduction
- Circuit Level Techniques
- Device Level Optimizations
- Leakage Reduction Techniques
- Multi-Threshold CMOS
- Variable-Threshold CMOS
- Transistor Stacking
- Gate level leakage reduction
- Ultra-Low Voltage Circuit Techniques
- Dynamic Threshold PMOS
- Active Leakage Power Management Techniques
- Energy Efficient Dynamic Circuits
- Robust and Efficient DVS
, dynamic voltage scaling
, Domino Logic
, low power CMOS
, switching power
Submitter: EE HomePage Editorial Staff
1189356050 (single entry page
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