| Name | Type | Details |
| Power Management Design Line | Web-Site |
Description: A CMP United Business Media web site devoted to power management issues.
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Author(s): Various License: Commercial Format: HTML Price: free URL: http://www.powermanagementdesignline.com/ ReviewText: Appears to be targeted primarily at engineers doing design at the board level. Keywords: low power , power management Submitter: EE HomePage Editorial Staff Affiliation: Reader xml_ID: 1156622915 (single entry page) |
| Save Those Watts With A Power-Aware Design Flow For SoCs | Article |
Description: A very good article that discusses the myriad of issues that must be dealt with when designing SoCs with internal power management features.
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Author(s): Bhatnagar, Mohit & Erickson, Jack & Iyer, Anand & McCrorie Pete License: Commercial Format: Paper, HTML Price: free URL: http://www.electronicdesign.com/ Articles/ ArticleID/ 12946/ 12946.html Keywords: low power , EDA , SoC , clock gating , 90nm , 65nm , power switches , level shifting , state retention register , latch-up , DVFS , AVS , dynamic voltage scaling Submitter: EE HomePage Editorial Staff Affiliation: Reader xml_ID: 1156622448 (single entry page) |
| Portable Design | Magazine/Journal |
Description: Targets design of portable electronic devices.
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License: Commercial Format: Paper Price: free if you qualify URL: http://www.portabledesign.com Limitations: Issues have been running fairly short (Mar2006 was only 32 pages). But still provides a nice way to survey this space and gain exposure to areas you might not normally have access to. ReviewText: After cancelling a number of other publications, I still check out Portable Design each month. Keywords: portable , low power Submitter: EE HomePage Editorial Staff Affiliation: Reader xml_ID: 1144296774 (single entry page) |
| Asynchronous Circuit Design: A Tutorial | Book |
Description: From the book's preface: "This book was compiled to address a perceived need for an introductory text
on asynchronous design. There are several highly technical books on aspects of
the subject, but no obvious starting point for a designer who wishes to become
acquainted for the first time with asynchronous technology."
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Author(s): Sparso, Jens & Furber, Steve License: Some Restrictions (includes GNU) Format: PDF Price: Free for non-commercial use URL: http://www.ee.technion.ac.il/ courses/ 048878/ book.pdf Limitations: may be used unmodified and in its entirety for non-commercial educational purposes only. ReviewText: This is a 182 page draft copy. Keywords: low power , EMI , logic design , dual rail logic , asynchronous design , handshaking , Muller pipeline Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1174192664 (single entry page) |
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