| Name | Type | Details |
| Fundamentals of Electrical Engineering and Electronics |
Description: This textbook has been restructured as a downloadable HTML help file.
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Author(s): Kuphaldt, Tony R. License: Some Restrictions (includes GNU) Format: HTML Price: Free URL: http://www.vias.org/ feee/ ReviewText: Contents include
Keywords: power factor , BJT , DAC , filters , Ohm's Law , Kirchhoff's Laws , complex numbers , reactance , resonance , JFET , binary arithmetic , boolean algebra , Karnaugh mapping , resistor color codes , algebra , trigonometry , calculus , Spice , transmission lines , amplifiers , magnetism , capacitors , transistors , electron tubes , tubes , transformers , counters , shift registers , power systems , semiconductors , thyristors , inductors , multivibrators , schematic , diodes , electrical safety , scientific notation , metric prefixes , series and parallel circuits , divider circuits , series-parallel combination circuits , dc metering circuits , dc network analysis , batteries , conductors , , insulators , electromagnetism , RC time constant , L/R time constant , time constant , polyphase ac circuits , ac metering circuits , ac motors , solid-state device theory , rectifiers , bipolar junction transistors , junction field-effect , insulated-gate field-effect transistors , IGFET , operational amplifiers , numeration systems , switches , electromechanical relays , ladder logic , digital-analog conversion , digital communication , conductor table , insulator tables , symbols , periodic table of the elements Submitter: EE HomePage Editorial Staff Affiliation: Employee xml_ID: 1168103854 (single entry page) |
| Name | Type | Details |
| Alli@nce VLSI CAD System | VLSI Development |
Description: The Alli@nce homepage says it best: "Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.
"
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License: Open Source, GNU or similar Price: free URL: http://www-asim.lip6.fr/ recherche/ alliance/ doc/ design-flow/ tools.html OSs: Windows, Linux, Solaris, Source Available Limitations: Binaries, source code and cell libraries are available under the GNU General Public License (GPL). ReviewText: The Alli@ance Tools Overview page does a great job of specifying the strengths and weaknesses of each tool in the CAD system. We'll limit ourselves here to simply listing the tools:
Keywords: VHDL , CIF , GDS , simulator , place & route , CAD , DRC , RTL , schematic , standard cells , RAM , ROM , Alliance CAD , formal proof , formal verification , logic synthesis , data-path , netlist extraction , FSM , layout editor , equivalence checker Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1150681894 (single entry page) |
| CircuitLogix | Schematic design & simulation |
Description: CircuitLogix is a Spice-based simulation package that appears to be targeted at the educational marketplace. A free student version is can be downloaded by students for use on their own machines. See the CircuitLogix web site for license restrictions.
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License: Commercial Price: $249 for single user license. Student version available for free to qualified users. URL: http://www.circuitlogix.com/ index.html OSs: Windows Limitations: Notes from the CircuitLogix site include: "The student version of CircuitLogix electronics lab simulation is available free of charge to any student studying electronics through an educational institution. The CircuitLogix Student Version is the same product as the full version of CircuitLogix with the following limitations:
ReviewText: As we're not students, we didn't download the software for review purposes. The web link we've provided appears to be the student version of the same tool listed at http://www.logicdesign.com/. The Logic Design web site also notes "In addition to electronic components, CircuitLogix also features a wide variety of electro-mechanical devices and includes innovative features such as advanced motor control, process control, and relay logic components.". Keywords: Spice , simulation , schematic , LTSPICE , mixed-mode simulation Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1181704541 (single entry page) |
| Kicad | Schematic capture and PCB layout |
Description: Kicad is an open source (GPL) software for the creation of electronic schematic diagrams and printed circuit board artwork
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License: Open Source, GNU or similar URL: http://www.lis.inpg.fr/ realise_au_lis/ kicad/ index.html OSs: Windows, Linux, Mac-OS Limitations: None Keywords: EDA , PCB , layout , schematic , circuit Submitter: Ian Bell Affiliation: User xml_ID: 1149576982 (single entry page) |
| gschem | Schematic Capture |
Description:
Schematic Capture Tool: Part of the gEDA project, gschem is a general purpose schematic capture program
designed to work in conjunction with other tools in the gEDA toolset.
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License: Open Source, GNU or similar Price: Free URL: http://geda.seul.org/ tools/ gschem/ index.html OSs: Linux Limitations: GNU General Public License version 2 (GPL) Keywords: schematic , gEDA Submitter: Mike Stanley Affiliation: None xml_ID: 20060317 (single entry page) |
| gsymcheck | Schematic Capture |
Description:
Symbol Checker: Part of the gEDA project, gsymcheck validates that symbols will work in gschem and related tools.
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License: Open Source, GNU or similar Price: Free URL: http://geda.seul.org/ tools/ gsymcheck/ index.html OSs: Linux Limitations: GNU General Public License version 2 (GPL) Keywords: schematic , gEDA , gschem Submitter: Mike Stanley Affiliation: None xml_ID: 20060319 (single entry page) |
| GOF: Gates On the Fly | netlist processing |
Description: GOF is a graphical netlist processing tool which integrates a netlist browser, partial schematic and ECO capability.
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License: Commercial Price: free for personal or educational use URL: http://www.nandigits.com/ home.htm OSs: Windows, Linux Limitations: A license for commercial use is $50. ReviewText: Has features for isolating logic cones. Can interface to waveform viewers (Verdi and GTKWave). Keywords: Verilog , RTL , schematic , Verdi , GTKWave , netlist , ECO Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1158117482 (single entry page) |
| gattrib | Netlist Generation |
Description:
Attribute Checker: Part of the gEDA project, gattrib reads a set of gschem schematic files and
creates a spreadsheet showing all components and associated attributes.
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License: Open Source, GNU or similar Price: Free URL: http://geda.seul.org/ tools/ gattrib/ index.html OSs: Linux Limitations: GNU General Public License version 2 (GPL) Keywords: spreadsheet , schematic , netlist , gEDA , gattrib Submitter: Mike Stanley Affiliation: None xml_ID: 20060310 (single entry page) |
| gnetlist | Netlist Generation |
Description:
Part of the gEDA project, this tool converts gschem files into a number of formats: Unix PCB, Spice, Verilog
VHDL and many others.
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License: Open Source, GNU or similar Price: Free URL: http://www.geda.seul.org/ tools/ gnetlist/ index.html OSs: Linux Limitations: GNU General Public License version 2 (GPL) ReviewText: You can now get the full gEDA suite of tools for Linux at http://www.geda.seul.org/download.html Keywords: Verilog , Spice , PCB , schematic , netlist , gEDA , gschem Submitter: Mike Stanley Affiliation: None xml_ID: 20060315 (single entry page) |
| LAyout System for Individuals (LASI) | layout editor |
Description: The LASI website states "LASI (LAyout System for Individuals) is a "general purpose" IC layout and design system. It was not specifically intended for CMOS logic circuits, but most people use it for that purpose. LASI can also draw and analyze schematics and do a simple LVS. It can also be used for PC boards and documentation drawings, but it is not really optimized for elaborate mechanical or architectural drawings."
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License: Restricted - see web site for details Price: A $5 donation is suggested for non-commercial use URL: http://members.aol.com/ lasicad/ index.htm OSs: Windows Limitations: A $99 single installation fee is requested per commercial user. ReviewText: Not reviewed at this time. Keywords: Spice , IC , CAD , layout , schematic , LVS , LASI Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1153702338 (single entry page) |
| Electric VLSI Design System | IC Layout, Schematic Entry, Verilog, VHDL & FPGA Design |
Description: From their website: "The ElectricTM VLSI Design System is a complete Electronic Design Automation (EDA) system that can handle many forms of circuit design".
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License: Open Source, GNU or similar Price: Free URL: http://www.staticfreesoft.com/ index.html OSs: Windows Limitations: Java-based, so should run on any system with Java 1.3 or higher. ReviewText: They have an accompanying online text book at http://www.rulabinsky.com/cavd/ . Keywords: Verilog , VHDL , IC , FPGA , layout , schematic Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1145133163 (single entry page) |
| Libero FPGA Integrated Development Environment | Actel Integrated IDE for FPGA design |
Description: Actel's website states: "Libero Integrated Design Environment (IDE) is Actel's comprehensive software toolset for designing with all Actel FPGAs. From schematic and/or HDL design, synthesis and simulation, through floorplanning, place and route, timing constraints and analysis, power analysis, and program file generation."
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License: Commercial Price: 1 year eval license is free URL: http://www.actel.com/ download/ default.aspx OSs: Windows, Linux Limitations: Node-locked 1 year evaluation license is available from the Actel website. It took about 5 minutes for us to register and start installing the software. ReviewText: Includes professional tools for design entry (Verilog, VHDL and schematic), synthesis, simulation and more. Keywords: Verilog , VHDL , FPGA , synthesis , place & route , Actel , schematic , ModelSim , Synplify , Libero Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1176259815 (single entry page) |
No matching Orgs were found.
