| Name | Type | Details |
| OMG SysML Specification | Specification |
Description: The Systems Modelling Language (SysML) "is a domain-specific modeling language for systems engineering applications. It supports the specification, analysis, design, verification and validation of a broad range of systems and systems-of-systems. These systems may include hardware, software, information, processes, personnel, and facilities." SysML is both a subset and extension of UML specifically targeted at system designers. See the SysML.org site for more information about the SysML Open Source Specification Progect.
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Author(s): Various License: Some Restrictions (includes GNU) Format: PDF Price: free URL: http://www.sysml.org/ specs.htm Limitations: The specification includes an open source license for distribution and use. ReviewText: At the time of posting, the current version of the spec is: 1.0. Contents include:
Keywords: SysML , UML , Unified Modelling Language , system design , OMG , SysML.org Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1155505728 (single entry page) |
| Name | Type | Details |
| Telelogic Modeler | UML Modeling Tool |
Description: "Telelogic Modeler is a Unified Modeling Language (UML) 2.1 based embedded systems and software design environment. ... Modeler enables users to improve communication by specifying, visualizing and documenting their system and software designs using a standard graphical language."
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License: Commercial Price: Free URL: http://www.ilogix.com/ sublevel.aspx? id=1756 OSs: Windows Limitations: There is a "Corporate Edition" at $100 per seat (100 seat minimum) that adds email support and integration with CM systems. ReviewText: EE Times did a nice article on this tool: Free modeling tool aims for small companies. Keywords: UML , system design , modeling , Rhapsody Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1170217756 (single entry page) |
| GreenSocs ESL Effort | Open Source ESL |
Description: The GreenSocs web site provides collaboratively developed, peer reviewed, ESL interfaces and infrastructure. Contents include GreenBus ("a versatile SystemC framework with which to model busses") and associated Spirit generator, DUST analysis framework for SystemC, a SystemC parser, and more.
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License: Open Source, GNU or similar Price: Free URL: http://www.greensocs.com/ OSs: Linux ReviewText: This appears to be a fairly ambitious project to develop open source ESL tools oriented around SystemC, Spirit, and other standards. We haven't tried any of the downloads, and cannot comment on how far the tool set (developed using SourceForge) has progressed. Keywords: SystemC , ESL , simulation , PCI , system design , AMBA , Spirit Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1182041035 (single entry page) |
| SPARK C-to-VHDL high-level synthesis framework | High level synthesis |
Description: "SPARK takes behavioral ANSI-C code as input, schedules it using speculative code motions and loop transformations, runs an interconnect-minimizing resource binding pass and generates a finite state machine for the scheduled design graph. Finally, a backend code generation pass outputs synthesizable register-transfer level (RTL) VHDL. This VHDL can then by synthesized using logic synthesis tools into an ASIC or by mapped onto a FPGA.
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License: Restricted - see web site for details Price: free for non-commercial use URL: http://mesl.ucsd.edu/ spark/ OSs: Windows, Linux, Solaris Limitations: This software is Copyright 2003-2004 The Regents of the University of California. All Rights Reserved. Permission to use, copy, modify, and distribute this software and its documentation for educational, research and non-profit purposes, without fee, and without a written agreement is hereby granted, provided that the above copyright notice, this paragraph and the following three paragraphs appear in all copies. Permission to incorporate this software into commercial products or for use in a commercial setting may be obtained by contacting: Technology Transfer Office
Support for fixed point math appears to be limited to specifying precision for built-in C datatypes. The tool is downloadable from the University of California at San Diego website, and is backed up by a number of academic publications. |
| C to Verilog | High level synthesis |
Description: C to Verilog is an easy to use web-based service which accepts a C language description of your datapath and generates synthesizable Verilog output.
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License: Commercial Price: free URL: http://www.ctoverilog.com OSs: Other Limitations: C-to-Verilog provides a free on-line service which allows users to compile their existing C code into optimized RTL. This RTL can be synthesized into an FPGA. They provide this service to demonstrate their technology. Companies who wish to license their technology or individuals who wish to make commercial use of the service can contact them. Application examples include:
Synthesis parameters appear to be globally applicable, and include:
Commercial tools may give you more control over your generated output, but if you have a limited budget and a need to quickly generate code for an FPGA application, then you should check out C to Verilog. |
No matching Orgs were found.