| Name | Type | Details |
| Implementation of a DFM checker for 65nm and beyond | Article |
Description: This is a nice five page introduction (from the EDA Tech Forum) to Design for Manufacturability at 65nm and below by engineers at the Crolles2 Alliance (Freescale Semiconductor, NXP Semiconductors and STMicroelectronics).
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Author(s): Le Maitre, P. & Simon, P. & Goncalves, R & Le Cam, L. & de Vries, D. & Bernard-Granger, F. & Parmentier, F. & Bingert, R. & Marin, J.-C. & Boone, R. & Hours, X. License: Commercial Format: Paper, PDF Price: Free URL: http://www.edatechforum.com/ journal/ june2007/ implementation_intro.cfm Limitations: You will have to register on the EDA Tech Forum web site to gain full access to the article (free). ReviewText: This article introduces DFM metrics and guidelines and discusses how improving one metric may adversely affect others - and how to hit the optimal mix. Keywords: SoC , DRC , DFM , design for manufacturability , yield , design rule checks , Calibre Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1180237119 (single entry page) |
| Name | Type | Details |
| InCyte Lite | Chip Estimation |
Description: ChipEstimate.com offers a free version of their InCyte chip estimation tool. Their website states "The system is used by thousands of chip planners to assess project feasibility, compare different IP configurations and to see the impact of new process nodes and IP on new and existing designs. Users input a high level design specification and InCyte Lite produces industry average estimations of chip die size, power, and leakage. Models used for estimation are built based upon averages from leading foundries and IP library suppliers. InCyte provides industry average estimation of the following key metrics:
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License: Commercial Price: Free URL: http://www.chipestimate.com/ incytelite.html OSs: Windows Limitations: In addition to InCyte Lite, there are two other versions of the tool available for purchase. Page 2 of the InCyte Datasheet has a chart comparing the features. Keywords: packaging , yield , leakage , SoC design , die size , power consumption , die cost , estimation Submitter: EE HomePage Editorial Staff Affiliation: User xml_ID: 1198716222 (single entry page) |
No matching Orgs were found.