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Name EntryDate Details
Design and Testing of a Simple GALS Circuit 2007-01-29 19:19:57 Description: This 42-page academic report describes the design of a Globally Asynchronous Locally Synchronous (GALS) design.
Author(s): Blaauwendraad, Bart
License: Some Restrictions (includes GNU)
Type: White Paper
Format: PDF
Price: free
URL: http://www.google.com/ url? sa=t& amp;ct=res& amp;cd=10& amp;url=http% 3A% 2F% 2Fwww.diva-portal.org% 2Fdiva% 2FgetDocument% 3Furn_nbn_se_liu_diva-1258-1__fulltext.pdf& amp;ei=aLe-RcylIIX8ggOqmKSYCw& amp;usg=__CvsVRe5aOBveM8uQoG55vd7BDw4=& amp;sig2=BvCJ1kP2Zsw2hC-FHZn4XA
Keywords: GALS , asynchronous logic , synchronous logic , Muller C-element , BIST , globally asynchronous locally synchronous , IDDQ , scan-path testing , stuck-at , stuck-open
Submitter: EE HomePage Editorial Staff
Affiliation: None
xml_ID: 1170127197 (single entry page)