| Name | EntryDate | Details |
| Alli@nce VLSI CAD System | 2006-06-18 19:51:34 |
Description: The Alli@nce homepage says it best: "Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router.
" License: Open Source, GNU or similar Type: VLSI Development Price: free URL: http://www-asim.lip6.fr/ recherche/ alliance/ doc/ design-flow/ tools.html OSs: Windows, Linux, Solaris, Source Available Limitations: Binaries, source code and cell libraries are available under the GNU General Public License (GPL). ReviewText: The Alli@ance Tools Overview page does a great job of specifying the strengths and weaknesses of each tool in the CAD system. We'll limit ourselves here to simply listing the tools:
Keywords: VHDL , CIF , GDS , simulator , place & route , CAD , DRC , RTL , schematic , standard cells , RAM , ROM , Alliance CAD , formal proof , formal verification , logic synthesis , data-path , netlist extraction , FSM , layout editor , equivalence checker Submitter: EE HomePage Editorial Staff Affiliation: None xml_ID: 1150681894 (single entry page) |