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Name EntryDate Details
SPARK C-to-VHDL high-level synthesis framework 2009-07-04 14:29:35 Description: "SPARK takes behavioral ANSI-C code as input, schedules it using speculative code motions and loop transformations, runs an interconnect-minimizing resource binding pass and generates a finite state machine for the scheduled design graph. Finally, a backend code generation pass outputs synthesizable register-transfer level (RTL) VHDL. This VHDL can then by synthesized using logic synthesis tools into an ASIC or by mapped onto a FPGA. "
License: Restricted - see web site for details
Type: High level synthesis
Price: free for non-commercial use
URL: http://mesl.ucsd.edu/ spark/
OSs: Windows, Linux, Solaris
Limitations: This software is Copyright 2003-2004 The Regents of the University of California. All Rights Reserved.

Permission to use, copy, modify, and distribute this software and its documentation for educational, research and non-profit purposes, without fee, and without a written agreement is hereby granted, provided that the above copyright notice, this paragraph and the following three paragraphs appear in all copies.

Permission to incorporate this software into commercial products or for use in a commercial setting may be obtained by contacting:

Technology Transfer Office
9500 Gilman Drive, Mail Code 0910
University of California
La Jolla, CA 92093-0910
(858) 534-5815
invent@ucsd.edu
ReviewText: This is one of the few free tools we've found which allows you to define your algorithm directly in C and then translate that code into synthesizable VHDL. The last posted version of Spark is dated May 2005, so it doesn't appear to be actively supported. We had a few hickups when we ran it, but we were able to generate VHDL for a simple datapath.

Support for fixed point math appears to be limited to specifying precision for built-in C datatypes.

The tool is downloadable from the University of California at San Diego website, and is backed up by a number of academic publications.
Keywords: VHDL , C programming , synthesis , system design , RTL , logic synthesis
Submitter: EE HomePage Editorial Staff
Affiliation: None
xml_ID: 1246732175 (single entry page)